Marvell Technology Group

Marvell offers a broad, innovative portfolio of data infrastructure semiconductor solutions spanning computing, networking, security, and storage. Our products are essential to the required transformations the carrier, enterprise, data center and automotive data infrastructure market segments must achieve to advance the emerging services and applications of the proliferating data economy. To deliver the data infrastructure technology that connects the world, we’re building solutions on the most powerful foundation: our partnerships with our customers. Trusted by the world’s leading technology companies for over 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Our success is dependent on the tenacity of our global team coming together to lead that change. At Marvell, everyone has an important role to play in changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better. Visit https://www.marvell.com/

Jobs by Marvell Technology Group


Senior Staff Static Timing Analysis (STA) Engineer

Location: Burlington, Vermont

Type: full-time

Education: batchelors

Experience: 5-10yrs

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Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact The Compute Custom and Storage (CCS) team at Marvell is seeking candidates for a Senior Staff Static Timing Analysis (STA) engineering position. Common projects within CCS range from artificial intelligence and machine learning, to wired and wireless infrastructure, with the latest technology nodes. The team utilizes the latest EDA software tools, and work through the technical challenges to insure we meet the performance, power, and area requirements of the design. This position will work in tandem with the Physical Design, Design For Test, and other teams both at a local and global level.   What You Can Expect
  • In this hybrid role at a CCS site, you will be a Timing Sub-System/Partition Lead, responsible for timing closure at your hierarchical level, and all blocks within
  • Work with design teams across various disciplines such as DFT, RTL, and IP in the process of iterative timing feedback and closure
  • Deliver to the SoC level all necessary collateral of your sub-system/partition per the required schedule
  • Conduct and adjust timing correlation between PD tools and signoff, along with participating in early feasibility studies
  • Provide pushdown timing ECOs to blocks within the sub-system/partition
  • Work closely with the block level PD engineers in debugging and resolving timing issues at their level, but also interface timing at the sub-system/partition level
  • Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes
  • Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation
  • Responsible for managing tool independent timing constraints that will work for synthesis, place & route and static timing analysis
What We're Looking For  
  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. OR  Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
  • 3 years practical experience in Timing Analysis and Closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level
  • Worked in the latest technology nodes, and experience in advanced timing concepts such as SI, CDC, LVF, POCV, and MIS
  • Good understanding of Verilog/VHDL, along with general digital logic and architecture
  • Proficient at running sub-system (ie. partition) level timing signoff
  • Proficient in UNIX, and shell based scripting
  • Knowledge and Experience in both TCL and Python languages
  • Have some proficiency in Synthesis and Physical Design
  • Diligent, detail-oriented, and able to handle assignments with minimal supervision
  • Must possess good communication skills, be a self-driven individual and a good team player
  • Familiar and experienced with the balancing the trade-offs of Performance, Power, and Area
  Preferred Qualifications (in addition to the minimum qualifications)
  • 5 years practical experience in Timing Analysis and Closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level
  • Leading timing closure effort with a small team of engineers
  • Practical experience with Synopsys Timing Tools, such as Primetime and Tweaker
  • Experience in timing methodology and flow development
   

Principal Power Integrity Engineer (EMIR)

Location: Burlington, Vermont

Type: full-time

Education: batchelors

Experience: 5-10yrs

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Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.   At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.   Your Team, Your Impact   The Compute Custom and Storage (CCS) team at Marvell is seeking candidates for a Principal Power Signal Integrity (PSI) engineering position. Commonly referred to as ASIC/SOC Power Analysis, Power Integrity Signoff or EMIR. Projects within CCS range from artificial intelligence and machine learning, to wired and wireless infrastructure, with the latest technology nodes. The team utilizes the latest EDA software tools, and work through the technical challenges to insure we meet the performance, power, and area requirements of the design. This position will work in tandem with the Physical Design, Timing, and other teams both at a local and global level.   What You Can Expect
  • In this hybrid role at a CCS site, you will be responsible for Power Integrity analysis and signoff for Static/Dynamic IR and EM at the SoC level
  • Work with a variety of other disciplines and leaders in Physical Design, Integration, and Timing
  • Define SoC power targets with the technical lead, including coordination with package team
  • Managing and working with tool vendors on any related issues of the tool, or bring-up of the tool on a design
  • Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes
  • Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation
  • Responsible for managing tool and flow settings to insure the team is setup for success during analysis
What We're Looking For
  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
  • 5 years practical experience in Power Integrity Signoff (SoC level EMIR) and closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level
  • Practical knowledge and experience on running, debugging, and providing solutions for Static and Dynamic IR and EM at all levels of SoC hierarchy
  • Worked with both vector-less and vector modes of analysis at different phases of the SoC development
  • Have collaborated with Physical Design team on strategies and techniques to reduce risks with IR and EM, in a correct by construction style
  • Familiar with low power concepts and UPF, such as power gating and shutoff as it relates to power delivery and analysis
  • Have some proficiency in Circuit, Physical Design and Timing
  • Proficient in UNIX, and shell based scripting
  • Knowledge and Experience in both TCL and Python languages
  • Diligent, detail-oriented, and able to handle assignments with very little supervision
  • Must possess good communication skills, be a self-driven individual and a good team player
  Preferred Qualifications (in addition to the minimum qualifications)
  • 10 years practical experience in Power Signal Integrity (ie. SoC level EMIR) and Closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level
  • Practical experience with Cadence Voltus family of Signoff tools
  • Collaborated with Physical Design team on correlating Early Rail Analysis in PD tools, with results from Signoff
  • Have led a small team of PSI/EMIR engineers on SoC signoff, coordinating with PD and Timing
  • Have been involved in developing the Power Distribution Network (PDN) power grid for an SoC
  • Have led or participated in Power Integrity Signoff methodology and flow development
  • Knowledge and experience with verifying electromigration limits and fixing electromigration related failures

Senior Staff Physical Design and Integration Lead

Location: Burlington, Vermont

Type: full-time

Education: batchelors

Experience: 5-10yrs

See Full Listing
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.   At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.   Your Team, Your Impact   The Compute Custom and Storage (CCS) team at Marvell is seeking candidates for a Senior Staff Physical Design and Integration Lead engineering position. Projects within CCS range from artificial intelligence and machine learning, to wired and wireless infrastructure, with the latest technology nodes. The team utilizes the latest EDA software tools, and work through the technical challenges to insure we meet the performance, power, and area requirements of the design. This position will work in tandem with the other Physical Design related teams, such as Timing, Physical Verification, Power Integrity and other teams both at a local and global level.   What You Can Expect
  • In this hybrid role at a CCS site, you will be the leader on a large complex sub-system/partition through all phases of the design
  • Responsible for floorplanning a sub-system/partition, pushing down block boundary and pin assignment to team members
  • Work with a variety of teams to pull in their required portion of the sub-system, such as DFT and clock distribution teams
  • Leading a small group of engineers at the block level, insuring they are progressing, meeting milestones on schedule and quality, and correct deliverables
  • Work closely with the block level PD engineers in debugging and resolving timing and routing issues across all hierarchical levels
  • Be an active team member on physical design methodology and flow development
  • Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes
  • Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation
    What We're Looking For  
  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. OR  Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
  • 3 years practical experience in physical design at all levels of hierarchy with multiple ASICs/SOCs
  • Physical design knowledge and experience, from netlist handoff to GDS tape-out
  • Extensive experience with floorplanning at a sub-system/partition level, considering boundary snap of power/technology and pin assignment
  • Proficient in running sub-system/partition level signoff, including physical verification (DRC and LVS), along with power integrity (EMIR)
  • Experienced leading a small team of block level engineers, coordinating at the sub-system/partition level
  • Good knowledge of Verilog/VHDL, and track record of collaboration with RTL team
  • Good understanding of digital logic and architecture
  • Proficient in UNIX, and shell based scripting
  • Knowledge and experience with TCL language
  • Diligent, detail-oriented, and able to handle assignments with minimal supervision
  • Must possess good communication skills, be a self-driven individual and a good team player
  Preferred Qualifications (in addition to the minimum qualifications)
  • 5 years practical experience as a leader of a small team at the sub-system/partition level for multiple ASICs/SOCs
  • Worked with timing and clock teams on planning and integration of high speed clock distribution
  • 5nm/3nm experience with floor planning
  • Floorplanning and Physical Design with Cadence Innovus
  • Physical Verification with Siemens Calibre
  • Power Integrity Signoff with Cadence Voltus
  • Peripheral IO Pad assignment and associated RDL
  • Bump assignment planning and collaboration with fullchip and package team
  • Experience with Analog IP integration and implementation
  • Knowledge and experience with Python language
  • Experience with low power design methodology and implementation
  • Have led or participated in Physical Design and Integration methodology and flow development

Signal Integrity / Power Integrity Engineer - Packaging

Location: Burlington, Vermont

Type: full-time

Education: batchelors

Experience: 5-10yrs

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Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.   At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.   Your Team, Your Impact   The Marvell Advanced Packaging team is responsible for supporting customers with package designs that meet challenging electrical requirements. Many of the new designs are requiring multi-chip and multiple component configurations with high speed IP requirements.   What You Can Expect As an Advanced Packaging SI/PI Engineer, you will be responsible of the following:
  • Evaluating designs for challenging electrical requirements
  • Close interaction with layout engineers and IP teams will be required to optimize the electrical performance.
  • Other simulation related tasks, such as new EDA tool evaluations, flow development & scripting for efficiency.
  Requirements include:
  • Knowledge of signal integrity and power integrity
  • Experience with power plane design, modeling and analysis using tools like PowerSI, SIwave
  • An understanding of circuit elements and simulation techniques
  • Experience with at least one of the following programming languages –tcl, Java, Python, Perl, Skill, C++
  • Ability to work with engineers in multiple locations and geographies
  • Strong communication, presentation and documentation skills
  The ideal candidate would have:
  • Experience with 2.5D/3D package development
  • Experience with VNA and TDR measurements for packages and PCBs characterization
  • Familiarity with packaging technologies, materials, package substrate design rules and assembly rules
  • Understanding, debugging and simulations of EMI/EMC problems
  What We're Looking For   Bachelor’s degree in Electrical Engineering or related fields and 5-10 years of related professional experience. Master’s degree and/or PhD in Electrical Engineering or related fields with 3-5 years of experience.

Package Design Engineer

Location: Burlington, Vermont

Type: full-time

Education: batchelors

Experience: 5-10yrs

See Full Listing
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.   At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.   Your Team, Your Impact   The Marvell packaging organization is responsible for supporting customers with advanced package designs that meet challenging electrical requirements. Many of the new designs are requiring multi-chip and multiple component configurations driving advanced technology requirements.   What You Can Expect As a Marvell Packaging Design Engineer, you will be responsible of the following:
  • Hands on physical implementation of package designs to align with product electrical design requirements and supplier manufacturing groundrules
  • Running of electrical and physical checking tools
  • Optimizing the package design process with new innovative solutions for efficiency and quality.
  This will require:
  • Close interaction with electrical simulation engineers to optimize the design
  • Close interaction with the operations team and fabrication suppliers to meet design for manufacturing requirements
  • Other related tasks, such as new design tool evaluations, flow development, libraries usage and maintenance
  The ideal candidate would meet the following requirements:
  • Design experience on flip chip packages
  • Proficient in Cadence APD
  • Familiar with interpreting electrical simulation results such as IR Drop reports and S-parameter data, ability to run basic checks
  • Able to organize their work to meet specific milestones
  • Able to work well in a team
  What We're Looking For   Bachelor’s degree in Electrical Engineering or related fields and 5-10 years of related professional experience. Master’s degree and/or PhD in Electrical Engineering or related fields with 3-5 years of experience.