Senior Staff Static Timing Analysis (STA) Engineer

Marvell Technology Group

Location: Burlington, Vermont

Type: Full Time

Education: Bachelor's Degree

Experience: 5 - 10 Years

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

The Compute Custom and Storage (CCS) team at Marvell is seeking candidates for a Senior Staff Static Timing Analysis (STA) engineering position. Common projects within CCS range from artificial intelligence and machine learning, to wired and wireless infrastructure, with the latest technology nodes. The team utilizes the latest EDA software tools, and work through the technical challenges to insure we meet the performance, power, and area requirements of the design. This position will work in tandem with the Physical Design, Design For Test, and other teams both at a local and global level.


What You Can Expect

  • In this hybrid role at a CCS site, you will be a Timing Sub-System/Partition Lead, responsible for timing closure at your hierarchical level, and all blocks within
  • Work with design teams across various disciplines such as DFT, RTL, and IP in the process of iterative timing feedback and closure
  • Deliver to the SoC level all necessary collateral of your sub-system/partition per the required schedule
  • Conduct and adjust timing correlation between PD tools and signoff, along with participating in early feasibility studies
  • Provide pushdown timing ECOs to blocks within the sub-system/partition
  • Work closely with the block level PD engineers in debugging and resolving timing issues at their level, but also interface timing at the sub-system/partition level
  • Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes
  • Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation
  • Responsible for managing tool independent timing constraints that will work for synthesis, place & route and static timing analysis

What We’re Looking For


  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. OR  Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
  • 3 years practical experience in Timing Analysis and Closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level
  • Worked in the latest technology nodes, and experience in advanced timing concepts such as SI, CDC, LVF, POCV, and MIS
  • Good understanding of Verilog/VHDL, along with general digital logic and architecture
  • Proficient at running sub-system (ie. partition) level timing signoff
  • Proficient in UNIX, and shell based scripting
  • Knowledge and Experience in both TCL and Python languages
  • Have some proficiency in Synthesis and Physical Design
  • Diligent, detail-oriented, and able to handle assignments with minimal supervision
  • Must possess good communication skills, be a self-driven individual and a good team player
  • Familiar and experienced with the balancing the trade-offs of Performance, Power, and Area


Preferred Qualifications (in addition to the minimum qualifications)

  • 5 years practical experience in Timing Analysis and Closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level
  • Leading timing closure effort with a small team of engineers
  • Practical experience with Synopsys Timing Tools, such as Primetime and Tweaker
  • Experience in timing methodology and flow development



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