Principal Power Integrity Engineer (EMIR)

Marvell Technology Group

Location: Burlington, Vermont

Type: Full Time

Education: Bachelor's Degree

Experience: 5 - 10 Years

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.


At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.


Your Team, Your Impact


The Compute Custom and Storage (CCS) team at Marvell is seeking candidates for a Principal Power Signal Integrity (PSI) engineering position. Commonly referred to as ASIC/SOC Power Analysis, Power Integrity Signoff or EMIR. Projects within CCS range from artificial intelligence and machine learning, to wired and wireless infrastructure, with the latest technology nodes. The team utilizes the latest EDA software tools, and work through the technical challenges to insure we meet the performance, power, and area requirements of the design. This position will work in tandem with the Physical Design, Timing, and other teams both at a local and global level.


What You Can Expect

  • In this hybrid role at a CCS site, you will be responsible for Power Integrity analysis and signoff for Static/Dynamic IR and EM at the SoC level
  • Work with a variety of other disciplines and leaders in Physical Design, Integration, and Timing
  • Define SoC power targets with the technical lead, including coordination with package team
  • Managing and working with tool vendors on any related issues of the tool, or bring-up of the tool on a design
  • Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes
  • Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation
  • Responsible for managing tool and flow settings to insure the team is setup for success during analysis

What We’re Looking For

  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience. OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience.
  • 5 years practical experience in Power Integrity Signoff (SoC level EMIR) and closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level
  • Practical knowledge and experience on running, debugging, and providing solutions for Static and Dynamic IR and EM at all levels of SoC hierarchy
  • Worked with both vector-less and vector modes of analysis at different phases of the SoC development
  • Have collaborated with Physical Design team on strategies and techniques to reduce risks with IR and EM, in a correct by construction style
  • Familiar with low power concepts and UPF, such as power gating and shutoff as it relates to power delivery and analysis
  • Have some proficiency in Circuit, Physical Design and Timing
  • Proficient in UNIX, and shell based scripting
  • Knowledge and Experience in both TCL and Python languages
  • Diligent, detail-oriented, and able to handle assignments with very little supervision
  • Must possess good communication skills, be a self-driven individual and a good team player


Preferred Qualifications (in addition to the minimum qualifications)

  • 10 years practical experience in Power Signal Integrity (ie. SoC level EMIR) and Closure on multiple ASICs/SOCs, at a block and sub-system (ie. partition) level
  • Practical experience with Cadence Voltus family of Signoff tools
  • Collaborated with Physical Design team on correlating Early Rail Analysis in PD tools, with results from Signoff
  • Have led a small team of PSI/EMIR engineers on SoC signoff, coordinating with PD and Timing
  • Have been involved in developing the Power Distribution Network (PDN) power grid for an SoC
  • Have led or participated in Power Integrity Signoff methodology and flow development
  • Knowledge and experience with verifying electromigration limits and fixing electromigration related failures

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