Timing Engineer Intern

Marvell Technology Group

Location: Burlington, Vermont

Type: Internship

Education: High School Diploma / GED

Experience: Less than 1 year

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Central Engineering ASIC Design Services in Marvell designs and develops chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure. We are looking for an Intern professional who will help with the design, analysis, and implementation of timing fixes on system-on-chip (SOC) designs.

Job Responsibilities:

  • Develop understanding the SOC design requirements and specification.
  • Develop understanding the computer-aided design (CAD) tools/flow defined for ASICs.
  • Design and Develop the SOC using Linux. TCL, Python/Perl (or other equivalent scripting languages).
  • Analyze, debug, and implement fixes for reported test timing associated with the designs.
  • Collaborate with global CAD teams on design flow fixes and feature improvements.

Requirements:

  • Candidate MUST be currently pursuing a BS/MS (preferred) degree in CS/EE or related technical field(s)
  • 0-1 years of previous experience
  • Knowledge of Industry standard Design tools
  • Knowledge of Physical Design  tools and experience in using them in a beginning-to-end project setting in recent semiconductor technology nodes – 5nm/7nm/10nm and 14nm/16nm are preferred but 28nm/32nm acceptable.
  • Excellent English communication skill in verbal and written.
  • Able to work effectively with global team and be self-motivated to solve problems.

More Information

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