Marvell Technology Group
At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.
The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.
The Central Engineering Test Chip Development team is responsible the hardware validation of custom SRAM, logic, IOs, and security circuits for Marvell business units in the latest semiconductor nodes. This is accomplished by designing test chips, providing a laboratory environment to collect hardware measurements, and working with the custom circuit design teams to complete the necessary circuit analysis for hardware validation.
- Logic design and verification through simulation (Verilog) of test chip experiments
- Verilog test pattern generation, simulation, and debug of test chip experiments in hardware
- Development of a laboratory environment to enable debug, diagnostics, and data collection of hardware measurements
- Software development: data processing with scripts (Perl, Python, tcl) for design, hardware characterization, laboratory measurements, and analysis of results
- Analyze, summarize, document, and present results
- Candidate MUST be currently pursuing a BS/MS degree in EE/CE or related technical field(s)
- 0-1 years of previous experience