Synthesis Engineering Intern

Marvell Technology Group

Location: Burlington, Vermont

Type: Internship

Education: High School Diploma / GED

Experience: Less than 1 year

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Central Engineering ASIC Design Services in Marvell designs and develops chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure. As a Synthesis Engineering Intern you will be developing and supporting a synthesis flow used by our customers for digital logic design in advanced semiconductor nodes (7nm and newer).

Job Responsibilities:

  • Perform logic synthesis and related analysis of output, with extended work to investigate prediction of downstream results
  • Work with logic design and PnR engineers on logic, timing, power and physical issues
  • Learn, implement, enhance, synthesis flow using using Linux. TCL, Python/Perl (or other equivalent scripting languages).
  • Collaborate with global CAD teams and contribute to the continuous development of IC design flow

Minimum Qualifications:

  • Aptitude for VLSI, proficiency with computers and Microsoft Office
  • Academic knowledge of area, speed, power optimizations during logic synthesis
  • Familiarity with IC design flow,  commercial implementation tools for logic synthesis (DC, Genus), synthesizable Verilog and/or VHDL codes
  • Excellent English communication skill in verbal and written
  • Able to work effectively with global team and be self-motivated to solve problems and manage deliverables.

Preferred Qualifications:

  • Thorough understanding of Linux/Unix, with experience working on Multi-threaded systems,
  • Excellent programming Skills in scripting languages (e.g., TCL, Python) in a Unix type environment, with good problem-solving skills.
  • Prior industry experience.

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