Staff Design for Test (DFT) Engineer

Marvell Technology Group

Location: Burlington, Vermont

Type: Full Time

Education: Bachelor's Degree

Experience: 3 - 5 Years

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Central Engineering ASIC Design Services in Marvell designs and develops chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure. Rigorous Design-for-Test (DFT) methods ensure that a part can be tested with an extremely high degree of fault coverage in a time-constrained manufacturing environment.

Job Responsibilities:

  • Develop understanding of both the block level and chip top design-for-test (DFT) and automated test pattern generation (ATPG) flows for complex custom ASIC designs
  • Execute DFT insertion and verification flows for scan test, Memory Built-in Self-Test (MBIST), and IP macro test
  • Execute digital logic, MBIST, and IP test pattern generation and simulation flows
  • Support manufacturing test hardware bring-up and pattern debug


  • Bachelor of Science degree in Computer Science, Electrical Engineering or related fields and at least 3-5 years of related professional experience, or Master of Science degree and/or PhD in Computer Science, Electrical Engineering or related fields and at least 2-3 years of related experience
  • 2+ years experience with third-party EDA DFT tools: Mentor Tessent, Cadence Modus, or Synopsys TestMAX
  • 2+ years and demonstrable hands-on experience with scan test, logic and memory BIST/BISR, functional test, JTAG, and other test methodologies
  • Demonstrable programming skills with C/C++, TCL/MySQL, or Perl/Python in Unix type environment, with good problem-solving skills
  • Effective teamwork and communication skills
  • Good understanding of Linux/Unix, with experience working on multi-threaded systems

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