Marvell Technology Group
At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.
The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.
MGS ASIC Design Center:
Marvell Government Solutions (MGS) designs and develops ASICs for customers in critical infrastructure sectors leveraging Marvell’s leading edge IP portfolio. We are looking for a Senior Staff Physical Design professional to support system-on-chip (SOC) implementation, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity analysis, and physical verification of designs to ensure successful tapeout and delivery to our customers.
As a member of the MGS Design Center you will have opportunities to:
- Work on leading-edge low power high performance designs in advanced technology nodes (14nm/12nm/7nm/5nm)
- Work closely with other functional teams at Marvell, across IP Design, Methodology, Packaging, Test, and Manufacturing
- Implement multi-core ARM SOCs, high speed interface designs using SerDes, PCI-e, DDR4, and low power design architectures
Minimum Qualifications for this requirement include:
Bachelor’s degree in Computer Science, Electrical Engineering or related fields, or the equivalent work experience that provides knowledge and exposure to relevant theories, principles and concepts.
- Eligibility for US DoD Security Clearance
- Minimum 3-5 years of leadership experience in semiconductors, ASIC/FPGA development, CAD, EDA, or custom circuit layout and design
- Successful tape-out of multiple custom silicon designs in advanced FinFet technology nodes
- Demonstrated design lead experience migrating products from FPGA platforms to custom ASIC implementations
- Deep experience with industry standard place & route flows
- Broad experience with EDA tools to support custom design, simulation, and layout
- Fluency developing scripts, programs, flows, and methodologies to automate and improve custom design productivity
- Expertise managing design tradeoff optimizations (Power/Performance/Area)
- In-depth knowledge of custom design environments from schematic capture, simulation, layout
- Advanced scripting skills in TCL/Python
- Familiarity with industry standard interfaces (PCIe, DDR)
- Excellent verbal and written English communication skills
- Fluency with Linux, version control tools, and Unix utilities
- Master’s degree in Computer Science, Electrical Engineering or related fields
- Thorough understanding of Linux OS internals, with ASIC development experience on multi-threaded systems
- Active US DoD Security Clearance