Senior Staff IP Integration Engineer

Marvell Technology Group

Location: Burlington, Vermont

Type: Full Time

Education: Bachelor's Degree

Experience: 5 - 10 Years

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Central Engineering ASIC Design Services in Marvell designs and develops chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure. Marvell provides end-to-end (from RTL to GDS) capabilities using the industry leading Design Automation software and flows to tape out designs to the world’s top fabs in 5nm and smaller geometries. The Senior Staff IP Integration Engineer will be responsible for the development and verification of custom logic that surrounds IP blocks to ease integration at an SOC level.

Job Responsibilities:

  • Provide technical guidance and direct effort to support a variety of IP integration tasks that enable soft and hard IP blocks to be integrated into an SOC.  Solutions are needed for a range of IP blocks, such as custom eFuse controllers for designs in 14nm, 7nm, 5nm and smaller geometries.
  • Specify, develop and lead implementation of custom logic solutions.  Leverage knowledge of and provide guidance on industry best practices for logic design and verification.
  • Align with project management team to meet project schedule and budget.
  • Collaborate with and lead a global development team.
  • Mentor other engineers in their domain area expertise.

Requirements:

  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience.
  • Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
  • Proven track record of leading custom logic development and block integration activities for complex SOC designs.
  • Strong logic design and/or logic design verification (UVM) skills.
  • In-depth understanding of semiconductor industry best practices and design techniques.
  • Automation minded and an expert familiar with modern scripting languages.
  • Detail oriented and self-motivated team leader with good verbal and written communication skills.
  • Knowledge of industry leading DFT Solutions; preferably Siemens Mentor Tessent or Synopsys TestMax.   Knowledge of IEEE 1687 a plus.
  • Knowledge of static timing closure methods.

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