Marvell Technology Group
Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Synthesizable IP team in Marvell’s Central Engineering group develops digital logic designs that supply high value-add to System-on-Chip Integrators. We have developed a variety of fully verified custom and configurable logic designs and offer design-to-spec logic design and verification services with quick design cycles. The group collaborates with other teams developing Analog/Mixed Signal (AMS) blocks as well as the overall chip designers to architect and propose solutions and owns the design through the hardware bring-up of the test chips and products.
What You Can Expect
The position involves working with the other members of the Synthesizable IP team to interpret input from potential clients and our CE AMS colleagues to propose digital solutions that will help add value to Marvell’s product offerings. Once a proposal is accepted, the design verification team will draw up a detailed verification plan based on the design specification – including architecture of the test bench, description of the required elements, and criteria for completion of the verification process. The team will then execute to the plan with rigor, providing detailed information to the designer for any bugs uncovered during the verification process, and ultimately providing a final report.
What We’re Looking For
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience.
Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
The candidate must be a self-starter with proven experience in architecting and developing SystemVerilog test benches for digital design verification. Experience with industry standard verification tools is essential: for example, Cadence XCelium. Skill in interpreting specifications and planning, along with the ability to debug is also critical. It’s highly preferable that the candidate have a working understanding of Verilog RTL and digital design techniques. A knowledge of a variety of industry specifications and protocols is also desirable.