Senior Staff DFT Engineer

Marvell Technology Group

Location: Burlington

Type: Full Time

Education: Batchelor's Degree

Experience: Greater than 10 years

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.


The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

 

The Opportunity

Central Engineering ASIC Design Services in Marvell designs and develops chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure. Rigorous Design-for-Test (DFT) methods ensure that a part can be tested with an extremely high degree of fault coverage in a time-constrained manufacturing environment.

 

Responsibilities:

  • Architect DFT solutions for complex custom ASIC designs and collaborate across the design and manufacturing test teams to implement those solutions
  • Lead teams in the execution of DFT insertion and verification flows for scan test, Memory Built-in Self-Test (MBIST), and IP macro test
  • Lead teams in the execution of automated test pattern generation (ATPG) and pattern simulation, meeting stringent fault coverage requirements
  • Support manufacturing test hardware bring-up and pattern debug
  • Contribute best practices and define improvements to the DFT flows
  • Represent Marvell DFT in customer-facing discussions

 

Requirements

  • Bachelor of Science degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience, or Master of Science degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience
  • Hands-on experience with scan test, logic and memory BIST/BISR, functional test, JTAG, and other test methodologies
  • Expert in industry standard scan test (including scan compression) and memory BIST/BISR tools
  • Expert in modern JTAG standards and implementation, including IEEE 1149 and IEEE 1687
  • Experience and knowledge of Synthesis, IC routing and static timing tools
  • Experience and knowledge of functional verification, especially of DFT features
  • Experience and knowledge of high-volume test equipment (ATE) and system-level test (SLT)
  • Proficiency with programming and scripting languages such as Perl/TCL

 

Other Skills:

  • Excellent teamwork, communication, analysis, and problem-solving skills
  • Strong knowledge of third-party EDA DFT tools (Mentor Tessent, Cadence Modus, or Synopsys TestMAX) and able to manage vendor relationships
  • Domain expert and mentor to less-experienced engineers
  • Good understanding of Linux/Unix, with experience working on multi-threaded systems 
  • Strong programming skills with C/C++, TCL/MySQL, or Perl/Python in Unix type environment
  • Inherent sense of urgency and accountability
  • Ability to multi-task in a fast-paced environment

 

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