Marvell Technology Group
At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.
The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.
Central Engineering ASIC Design Services in Marvell designs and develops chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure.
Rigorous Design-for-Test (DFT) methods ensure that a part can be tested with an extremely high degree of fault coverage in a time-constrained manufacturing environment.
Develop understanding of both the block level and chip top design-for-test (DFT) and automated test pattern generation (ATPG) flows for complex custom ASIC designs.
Execute DFT insertion and verification flows for scan test, Memory Built-in Self-Test (MBIST), and IP macro test.
Execute digital logic, MBIST, and IP test pattern generation and simulation flows.
Support manufacturing test hardware bring-up and pattern debug.
Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 3-5 years of related professional experience.
Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 2-3 years of experience.