Marvell Technology Group
At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.
The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.
About the Position:
Marvell Government Solutions (MGS) designs and develops ASICs for customers in critical infrastructure sectors leveraging Marvell’s leading edge IP portfolio. We are looking for an entry-level Physical Design professional to support system-on-chip (SOC) implementation, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity analysis, and physical verification of designs to ensure successful tapeout and delivery to our customers.
As a member of the MGS Design Center you will have opportunities to:
Work on leading-edge low power high performance designs in advanced technology nodes (14nm/12nm/7nm/5nm)
Work closely with other functional teams at Marvell, across IP Design, Methodology, Packaging, Test, and Manufacturing
Implement multi-core ARM SOCs, high speed interface designs using SerDes, PCI-e, DDR4, and low power design architectures
· Bachelor’s degree in Computer Science, Electrical Engineering or related fields, or the equivalent work experience that provides knowledge and exposure to theories, principles and concepts.
· Exposure on ASIC design, verification, Test, Physical implementation, Layout and Semiconductor device/process through previous work/intern experience or course work
· Experience with EDA tools and methodologies for one or more of the following, through course work or internship experience:
o Coding in SystemVerilog, Verilog, or C/C++ for testbench development,
o UVM or VMM or OVM verification methodologies,
o Design for Test (DFT) and simulation,
o Physical design and implementation
o RTL Synthesis
o STA Timing
o Low Power design optimization and reliability signoff,
o Custom layout and Physical verification using EDA tools
· Excellent verbal and written English communication skills
· Able to work effectively with global team and be self-motivated to solve problems and manage deliverables
· Eligibility for US DoD Security Clearance
· Thorough understanding of Linux/Unix/BSD Internals, with experience working on Multi-threaded systems.
· Excellent programming Skills in scripting languages (e.g., TCL, Python) in a Unix type environment, with solid problem-solving skills.
· Active US DoD Security Clearance
· 1-3 years of prior industry experience in co-op or internship.