Physical Design Integration Engineer

Marvell Technology Group

Location: Burlington, Vermont

Type: Full Time

Education: Bachelor's Degree

Experience: 1 - 2 Years

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Work with a small, motivated team responsible for constructing an ASIC based physical integration flow for advanced CMOS technology nodes used by a worldwide design center for a diverse & complex customer set. Development opportunities exist in all technology nodes ranging from 14nm to 3nm.  The Marvell ASIC Business is expanding greatly, and this is a great opportunity to join an experienced team that needs to deliver rapid and innovative solutions to our customers.

This not only encompasses the standard place and route mechanics, but also developing physical block construction techniques ensuring highly hierarchical designs integrate successfully.  This also includes developing integration support for complex IP, both internally and externally developed, into our base place and route flow.  The basis for these tasks is to have a complete understanding of the base technology ground rules from the foundry, and help translate that into a repeatable, reliable ASIC physical design flow. The team you would be joining primarily focuses on development but works very close with the design center engineers using our flows to ensure success of each ASIC chip design.  We are involved from the initial ASIC chip sizing to the final physical verification before submission to the foundry for mask build. The ideas/tools we develop contribute directly to the ASIC business unit success.

Job Responsibilities:

  • Interpreting CMOS technology ground rules into physical Place and Route rules and guidelines.
  • Verifying Place and Route flows with physical verification decks.
  • Coding, documenting and releasing complex IP integration flows to chip design services.
  • Interacting with different chip integration teams within the company to develop best practices.
  • Define custom checking requirements for ASIC chip physical integration methods.


  • Bachelor’s degree in Computer Science, Electrical Engineering or related fields and at least 1-3 years of related professional experience. Master’s degree in Computer Science, Electrical Engineering or related fields with no professional experience.
  • Understanding of basic Place and Route techniques for CMOS technology gate level design.
  • Understanding of basic CMOS technology physical ground rules.
  • Familiarity with Cadence based Place and Route tools, primarily “Cadence Innovus”.
  • Detail oriented with good problem-solving skills.
  • Fluent with tcl based scripting.
  • Good communication/documentation skills along with team and cross-team interactions.
  • Good understanding of Linus/Unix Internals
  • Experience with Load Balancing technologies is a big plus.

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