Entry Level Professional – Timing Engineer (Summer 2024 Start)

Marvell Technology Group

Location: Burlington, Vermont

Type: Full Time

Education: Bachelor's Degree

Experience: 1 - 2 Years

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications.

What You Can Expect

  • Work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process.
  • Be hands on in triaging workflows, whether it’s running RTL code through synthesis and place and route (PnR) tools to create the physical view of the chip, analyzing performance by running timing analysis, verifying a robust power grid by performing EMIR analysis, etc.
  • Review completed runs for errors or create optimizations from successful runs in order to verify that the database is ready to move on to the next level

What We’re Looking For

To be successful in this role you must:

  • Have completed a Bachelor’s Degree in Electrical/Computer Engineering, Computer Science, or related fields and have 1-3 years of related professional experience OR a Master’s degree and/or PhD in Electrical/Computer Engineering, Computer Science, or related fields. In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis.
  • Have work or course experience where you created and tested a logic block, then were able to look at the quality of results to ID improvements.
  • Know formulas for timing analysis and concepts for synthesis and place and route.
  • Enjoy learning by doing the work and having access to guides and a mentor.
  • Be willing to raise your hand and volunteer for learning opportunities you may not have experienced before.

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