Marvell is looking for a passionate and innovative Digital Circuit Design Engineers to join our Central Engineering – Analog Mixed Signal (CE-AMS) group and be part of a team building state-of-the-art memory and hardware security. The team develops cutting-edge custom SRAM compilers, Physical Unclonable Functions, and Software to guide SoC memory usage in advanced FinFET semiconductor nodes.

Job Responsibilities:

As a Digital Circuit Design Engineer, you’ll be responsible for

• Design and implement custom digital and analog circuits

• Schematic entry (Cadence Virtuoso), Circuit Simulation (Spectre, MDL, Post-layout), Verification (Verilog)

• Statistical analysis of complex circuits across a wide Process, Voltage, Temperature (PVT) range

• Overseeing and coordinating IP evaluation (Silicon Validation) with Test and Characterization teams

• Helping develop the team and mentoring other engineers / interns

• Data summaries, documentation, and presentation of important information to a global team

Requirements:

Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or related fields and 0-2+ years of related professional experience in memory design and related fields.

Preferred qualifications

• Digital logic design and simulation

• Analog design and simulation experience

• Memory array design

• Knowledge of UNIX and CADENCE Virtuoso design environments (Schematic, Simulation, Post-Layout Extraction)

• EM/IR and Reliability analysis

• Memory verification using Verilog HDL

• Proficiency in scripting languages (Perl, Python, TCL, …)

• Motivated self-starter and good at multi-tasking

• Exceptional teamwork, communication, and leadership skills

• Publication in journals or conferences and/or patents a plus