Design For Test Engineer Intern

Marvell Technology Group

Location: Burlington, Vermont

Type: Internship

Education: High School Diploma / GED

Experience: Less than 1 year

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Central Engineering ASIC Design Services in Marvell designs and develops complex, custom chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure. The Design-for-Test (DFT) team is a global team that impacts chip design from inception all the way to manufacturing production. Rigorous DFT methods ensure that a chip can be tested with an extremely high degree of defect coverage in a time-constrained manufacturing environment, directly impacting product quality and customer satisfaction.

The ideal candidate will possess both digital logic design and verification skills along with software development and programming skills. Such a candidate will enjoy an opportunity that spans disciplines and involves them in all aspects of semiconductor chip design.


Job Responsibilities:

  • Develop understanding of the block level or chip top design-for-test (DFT) and automated test pattern generation (ATPG) flows for complex custom ASIC designs
  • Execute DFT insertion and verification flows for scan test, Memory Built-in Self-Test (MBIST), and IP macro test
  • Execute digital logic, MBIST, and IP test pattern generation and simulation flows
  • Analyze results and look for ways to improve test coverage
  • Collaborate with the global DFT team on design flow improvements


  • Currently pursuing a Bachelor of Science, Master of Science, or Ph.D. degree in Computer Science, Electrical Engineering, or related fields
  • Digital logic design skills with Verilog
  • Knowledge of scan-based logic test, memory BIST/BISR, functional test, JTAG, and other test methodologies is a plus
  • Demonstrable programming skills with Tcl, Python, Perl, or csh/bash in a Unix environment, with good problem-solving skills
  • Good understanding of Linux/Unix, with experience working on distributed systems
  • Effective teamwork and communication skills

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