Marvell Technology Group
Marvell’s ASIC Business Unit develops cutting-edge custom semiconductor solutions in the most advanced technologies. Our focus is on solving the most difficult design problems in the areas of AI, wired and wireless communications, and other infrastructure applications.
The ASIC BU is seeking a candidate with experience in the semiconductor industry along with a broad knowledge of the associated technical disciplines including wafer technology and manufacturing, physical design and common ASIC elements such as logic, arrays, analog cores and interfaces. That experience will be used to take functional requirements from ASIC customers to estimate physical die sizes and is a critical component of winning new business.
Wafer technology and chip design components are constantly evolving. A successful Custom Silicon Physical Architect will need not only broad working knowledge but also a commitment to continuous learning and good working relationships with technical specialists throughout the company.
The Custom Silicon Physical Architect works closely with all roles in the Quoting Team including IP, packaging, test, costing, and especially the customers. They are frequently called upon to give technical presentations to ASIC customers showing the basis for the quoted physical die size(s), the trade-offs, and the competitive advantages. A major goal is to differentiate Marvell ASICs from the competition with our understanding of customer requirements, planning, technical expertise, and willingness to be a partner.
The Custom Silicon Physical Architect is responsible for providing cost optimized chip sizings that meet customer RFQ requirements by:
- Collaborating with our team of Customer Solution architects
- Calculating physical die sizes that encompass contents, wiring requirements, layout, and placement restrictions
- Understanding and proposing alternative solutions when appropriate
- Enabling other Quote Team members that depend on the physical die sizings for their role in the quote process (Packaging, Test, Costing, and Product Management)
- Collaborating with the Design Center on the execution of chip designs after design award
- Identify and drive technical issues that affect current and future physical die sizes
- Partner across the ASIC BU on continuous improvement of tools and processes to enable and facilitate steady growth in revenue and market impact
- Bachelor’s degree in Electrical Engineering or related fields and 5-10 years of related professional experience.
- Master’s degree and/or PhD in Electrical Engineering or related fields with 3-5 years of experience.
- Proficiency in the use of Excel and Powerpoint
- Ability to prepare and present technical overviews
- Ability to multi-task, prioritize, and focus on the essentials to meet tight schedules
- Customer facing experience, internal and/or external
- Strong written and verbal communications
- A background in chip physical design. This brings an expertise to chip sizing for elements that are otherwise hard to quantify
- Team leadership and self-direction
- Project planning Software tools experience (Microsoft Project or similar)