ASIC Test Architecture Intern

Marvell Technology Group

Location: Burlington, Vermont

Type: Internship

Education: High School Diploma / GED

Experience: Less than 1 year

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Marvell Semiconductor is looking for an ASIC Test Architecture Intern. The qualified candidate will work as part of a multi-functional team to look at developing test solutions to meet the growing challenges of complex designs. Project focus areas could be but not limited to solutioning high performance device power demands under test, testing large multichip packaging designs, how to model power under test vs. functional power in the client applications and automation of predicting test times. Candidates will have the opportunity to gain exposure to the larger organization as a part of these tasks. Must be currently enrolled in an accredited university in an undergraduate or graduate degree program with an interest and aptitude to work in Electrical/Computer Engineering and technical communications.

Job Responsibilities:

  • Test data analysis with opportunity to create automated solutions
  • Understand power models for devices under test
  • Optimize test solutions for complex MCM designs

Minimum Requirements:

  • Candidate MUST be currently pursuing a BS/MS degree in CE/EE or related technical field(s)
  • 0-1 years of previous experience

Preferred Requirements:

  • Excellent design and development experience, pursuing a degree in CE/EE
  • Understanding basics of ATE semiconductor test
  • Structural vs functional
  • Die test vs final package test
  • Test fixtures/probe cards
  • Strong verbal and written communication skills
  • Demonstrated organized and thorough approach to documentation and design
  • Strong creative problem-solving skills
  • Knowledge of ASIC semiconductor industry is a plus

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