ASIC Physical Design Integration Engineer

Marvell Technology Group

Location: Burlington

Type: Full Time

Education: No Ed Requirements

Experience: 5 - 10 Years

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.


The Opportunity

Central Engineering ASIC Design Services in Marvell designs and develops chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure. Rigorous Physical Design (PD) methodologies are developed to ensure correct by construction flows along with integration of complex IP.


Responsibilities would include but not limited to:

  • Tcl coding to run under Cadence Innovus for various floorplan operations for P&R flow. This will inlcude base flow development changes across Marvell.
  • Develop Physical Design techniques for complex IP integration into existing ASIC design flow. This will include automation code to integrate within the flow as well as documentation.
  • Understand and become familiar with several foundry nodes base ground rules (GF 12LP, TSCM N7/N5)
  • Assist & support Design Center personal working on customer ASIC chips. Ensure successful tapeout commit dates.
  • Play active role with sharing best practices for Physical Design Techniques between different business units within Marvell.
  • Work with EDA vendors on issues found, future enchantments required.
  • Interface with IP development teams to influence IP contruction for better Place & Route integration.

Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience.

Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.


Experience and working knowledge of Cadence P&R EDA tooling especially Innovus.

Experience working in one or more of the following foundry nodes with Place and Route techniques, (TSCM N7/N5, GF 12LP)


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