ASIC Packaging Architecture Intern

Marvell Technology Group

Location: Burlington, Vermont

Type: Internship

Education: High School Diploma / GED

Experience: Less than 1 year

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.

The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

The Opportunity

Marvell Semiconductor is looking for an ASIC Packaging Architecture Intern. The qualified candidate will work as part of a multi-functional team to study next generation packaging including chiplets, 2.5D and 3D connected devices. Tasks will include: Defining multichip package solutions for high performance products, package layout, electrical simulation for signal and power integrity. Candidate will also have the opportunity to gain exposure to the wider organization as a part of these tasks. Must be currently enrolled in an accredited university in an undergraduate or graduate degree program with an interest and aptitude to work in Electrical Engineering and technical communications.

Job Responsibilities:

  • Package layout and electrical simulation for power and signal integrity
  • Package architecture tradeoff analysis (3D, 2.5D, MCM, design partitioning)

Minimum Requirements:

  • Candidate MUST be currently pursuing a BS/MS degree in CE/EE or related technical field(s)
  • 0-1 years of previous experience

Preferred Requirements:

  • Excellent design and development experience, pursuing a degree in CE/EE or related field[s]
  • Understanding of packaging of electronic components
  • Understanding of Signal and Power Integrity fundamentals
  • Strong verbal and written communication skills
  • Demonstrated organized and thorough approach to documentation and design
  • Strong creative problem-solving skills
  • Knowledge of ASIC semiconductor industry is a plus

More Information

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