ASIC Package Applications Engineer

Marvell Technology Group

Location: Burlington

Type: Full Time

Education: Master's Degree

Experience: 5 - 10 Years

At Marvell, we believe that infrastructure powers progress. That execution is as essential as innovation. That better collaboration builds better technology. Trusted by the world’s leading technology companies for 25 years, we move, store, process and secure the world’s data with semiconductor solutions designed for our customers’ current needs and future ambitions. Through a process of deep collaboration and transparency, we’re ultimately changing the way tomorrow’s enterprise, cloud, automotive, and carrier architectures transform—for the better.


The data infrastructure that our customers build has never been more critical to our global economy. It’s what’s keeping the world connected, businesses running, and information flowing. If you’re ready to excel, innovate, and truly enjoy your work, apply now for the position detailed below.

 

The Opportunity

Central Engineering ASIC Design Services in Marvell designs and develops chips for external customers in market segments ranging from artificial intelligence and machine learning to wired and wireless infrastructure. As part of our Central Engineering team, the team responsible for Marvell’s IP development, you will:

  • Develop Laminates/Packages for Artificial Intelligence applications and Networking Systems.
  • Have proven ability to use 2D,2.5D,3D techniques and abilities to develop future emerging industry leading package technologies
  • Demonstrated design ability in Single Chip and Multi-chip modules design.
  • Have experience with Industry Standard laminate analysis tools (Signal Integrity)
  • Work directly with Silicon design engineers.
  • Manage deliverables.
  • Bachelor of Science in Electrical Engineer, prefer Master’s of Science Electrical Engineer
  • Minimum 5 years of experience in semiconductor CAD, EDA, or custom design in both circuit and layout.
  • Experience working with communications chips.
  • Familiarity with industry standard interfaces.
  • Experienced with 2.5D packaging.
  • Knowledge of script writing in Perl/TCL/Python Cadence’s SKILL language. C/C++ a plus.
  • Have ability to use Linux OS, version control tools, and Unix utilities.
  • Excellent verbal and written communication skills.

 

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